1. Field of Invention
This invention relates to integrated circuit dynamic random access memories and in particular it relates to the circuitry for restoring the charge level in storage cells of a dynamic random access memory (dynamic RAM). The invention has particular application to metal oxide semiconductor (MOS) dynamic random access memory technology. In a dynamic random access memory, digital information is stored in the form of capacitance in a storage cell which can be addressed and sensed by conventional external circuitry. The charge increments in a group of selected storage cells are generally sensed by a set of cross-coupled transistor pairs each operative as a sense amplifier. The sense amplifier senses the charge on a capacitor in a memory cell by drawing off a portion of the charge during the sensing operation. Consequently, the signal level stored on the memory capacitor is degraded substantially after sensing is completed. Voltage degradation on the order of twenty percent of the maximum signal is typical.
Various circuits have been proposed to restore the charge on the memory cell to the maximum charge level. Among the proposed solutions are circuits for recharging the bit line while the transfer gate between the memory cell and bit line is on. Such charge restoration circuits have a number of disadvantages. For example, since the bit lines are very highly capacitively loaded when the transfer gates are on, charge restoration through the bit lines requires high power consumption and/or a relatively long time to recharge the cell. Second, since the charge restoration generally takes place through a transfer gate transistor, steps must be taken to assure that the transfer gate is fully on to assure maximum charge transfer to the storage cell. Consequently, the gating signal to the transfer gate transistor, typically designated the word line, must be held to a voltage level at least one threshold voltage level (diode drop) above the desired charging level. Finally, great care and attention must be given to the timing circuitry and control clocks to assure proper synchronization of the restore circuitry and the transfer gate driving circuitry.
What is needed is a circuit technique whereby the memory cell can be fully recharged without the identified disadvantages.
2. Description of the Prior Art
The operation of dynamic random access memories with a cross-coupled type of sense amplifier using a dummy cell and a capacitance storage cell is widely known and taught elsewhere. A few examples are U.S. Pat. No. 3,514,765 to Christensen entitled "Sense Amplifier Comprising Cross-coupled MOSFET's Operating in a Race Mode for Single Device Per Bit MOSFET Memories"; U.S. Pat. No. 3,678,473 to Wahlstrom entitled "Read-Write Circuit for Capacitive Memory Arrays"; a paper by John J. Barnes and John Y. Chan entitled "A High Performance Sense Amplifier for a 5V Dynamic RAM", published in IEEE Journal of Solid-State Circuits, Vol. SC-15, October 1980, pp. 831-838; a paper by Lee et al. entitled "A 80 ns 5V-Only Dynamic RAM", published in ISSCC Digest of Technical Papers, February 1979, pp. 146-147; and a paper by White et al. entitled "A 5V-Only 64K Dynamic RAM", in ISSCC Digest of Technical Papers, February 1980, pp. 230-231. These publications are representative of the developments in the state of the art related to sense amplifiers and dynamic random access memories.